This architecture is built around the concept of creating a processing pipeline, with each elemental signal processing algorithm being realized as an independent filter, and the entire signal processing requirements for a mode being realized by stringing together the required filters as a pipeline. The architecture is scalable in terms of different processing pipelines being able to be created in different processing cores, thus, allowing the radar system designer to add or subtract processor cores based on the processing needs.

Bringing in multiple processor cores brings in the additional challenges as the radar signal processing does switch between ranges-based processing to pulse-based processing. The other dimension of scalability that this architecture provides is the ability to add new signal processing steps or modes in form of new filters or pipeline.